1. Field of the Invention
The invention generally relates to semiconductor devices and manufacturing processes, and, more particularly, to methods of manufacturing semiconductor devices using wafers having a buried insulator layer such as silicon-on-insulator (SOI) wafers.
2. Description of the Related Art
In the manufacturing of semiconductors devices, SOI wafers or substrates are used to provide superior isolation between adjacent devices in an integrated circuit as compared to devices built into bulk wafers. SOI substrates are silicon wafers with a thin layer of oxide or other insulators buried in it. Devices are built into a thin layer of silicon on top of the buried oxide. The superior isolation thus achieved may eliminate the “latch-up” in CMOS devices and further reduces parasitic capacitances. In addition to the buried oxide layer, shallow trench isolations (STI) are often used to completely isolate transistors or other devices from each other.
Since the backside silicon substrate is completely decoupled from the devices, by means of the buried oxide, the voltage potential of the backside substrate tends to float during the operation of the circuit. This might influence the performance of the circuit and reduce the operation reliability.
To prevent the backside silicon substrate of the device from floating, dedicated contacts are formed to connect the backside substrate to a metal layer that has a defined potential. This conventional technique is illustrated in FIGS. 1a and 1b. 
Turning first to FIG. 1a, an SOI structure is shown that comprises a backside silicon substrate 100, a buried oxide layer 105 and a top silicon layer 110. Transistor structures 135, 140 are formed on top of the SOI structure. As is apparent from FIG. 1a, the top silicon layer 110 has isolation trenches 145, 150, 155 to decouple the transistor structures 135, 140 from each other and from further devices.
On top of the top silicon layer 110, the isolation trenches 145, 150, 155 and the transistor structures 135, 140, a silicon oxynitride (SiON) layer 120 is deposited that is used in subsequent etch processes as a stop layer. Further, between this etch stop layer 120 and the top silicon layer 110, suicides 115 may be formed.
Further, a TEOS (tetraethyl orthosilicate) layer 125 is deposited as a masking layer. Then, after the transistor structures 135, 140 and the contact stack of silicon oxynitride (SiON) and TEOS are formed, a resist layer 130 is patterned to provide a backside contact mask having an opening 160 for etching a contact to the backside silicon substrate 100.
Once the backside contact mask pattern is defined in the resist layer 130, the stack of tetraethyl orthosilicate (TEOS), silicon oxynitride (SiON), STI material and buried oxide is etched down to the backside silicon substrate 100. By this etching, a contact hole 165 is formed as shown in FIG. 1b. As is apparent from the figure, the isolation trench 145 is divided into two parts 170, 175 by forming the contact hole 165. The resist will now be removed by a plasma strip and an additional wet clean step.
Once the backside contact hole 165 has been formed, the formation of the contacts to connect the transistor structures 135, 140 takes place. This will require another resist layer pattern process and a separate etch step. Thus, the conventional technique involves a dual contact approach that requires a significant total etch process time and, thus, leads to high manufacturing costs.